1. Field of the Invention
The invention relates to digital electronic circuits, and more particularly, to synchronous circuits in which logic states are updated periodically in response to a clock signal.
2. Description of Related Art
Digital circuits are often designed for a synchronous operation. That is, they are intended to be used with a clock signal, and every time an effective edge of the clock signal occurs, the values on the outputs of the circuit are updated. The effective edge may be defined as the rising edge of the clock signal for some systems, and in other systems it may be defined as the falling edge.
Synchronous logic circuits are made up of data storage elements and combinational logic elements. The data storage elements may be any of a variety of different types of flip-flops such as D flip-flops, JK flip-flops and clocked T flip-flops. In a D flip-flop, the output is updated to equal the value which is on the D input at the time that the effective edge of the clock pulse arrives. In a JK flip-flop, the output is updated in response to the values on the J and K inputs at the time the effective edge of the clock pulse arrives, according to the following rules: If J=0 and K=0, the output remains unchanged; if J=1 and K=1, the output compliments; if J.noteq.K, the output is updated to match the value on the J input. In a clocked T flip-flop, the output remains unchanged if the T input is 0 when the effective edge of the clock pulse arrives, and toggles if the T input is high when the effective edge of the clock pulse arrives. Other types of flip-flops may also be used, and different types of flip-flops may be used in the same system.
The synchronous design philosophy for digital circuits has been generalized and formalized into what is known as the state machine model. In this model, all storage elements in a machine (which may make up part or all of a larger apparatus) are thought of as forming a "present state vector" describing the state of the machine at any given time. More specifically, assuming each storage element stores and outputs a single bit of information, the values on the outputs of all the storage elements form the present state vector of the machine being modeled.
Also in the state machine model, each storage element has one or more data inputs. A D-type storage element, for example, has only one data input, whereas a JK-type storage element has two (J and K).
The state machine model also contains "next state" circuitry, which generates a "next state vector", for applying to the storage elements. The next state circuitry or logic is a purely combinational logic circuit which generates the next state vector outputs as a purely combinational function of one or more elements of the present state vector and/or one or more separate inputs to the machine. Each output of the combinational circuitry is connected to a respective one of the inputs of the storage cells. As used herein, the "next state vector" is made up of the set of values applied to the inputs of the storage cells, even if two or more of the next state vector values are applied to each storage cell (as in the case of JK storage cells). Also as used herein, the term "combinational" can refer to a circuit as simple as a conductor or as complex as a many-level sequence of logic gates. In the state machine model, the outputs of the machine are also generated by the combinational logic circuitry as a function of the present state and/or the separate input signals. Since the term "combinational" includes a simple conductor, this model includes machines in which the outputs come directly from the outputs of one or more of the storage elements, as well as machines in which the outputs are a combinational function of the present state vector, the next state vector, and/or external inputs to the machine.
Some systems are designed using level-triggered storage elements such as latches, instead of edge-triggered storage elements such as flip-flops. In some of these systems, certain latches are transparent when the clock signal is high and opaque when the clock signal is low, and other latches are transparent when the clock signal is low and opaque when the clock signal is high. These systems require careful design to ensure that no race conditions can occur in which a change in the output of a transparent latch element propagates through combinational circuitry back to the input of the latch before the latch becomes opaque on the next clock transition.
Synchronous logic design has been used effectively for an extraordinary number of simple and complex systems. In integrated circuit design, a system may be incorporated onto one or more integrated circuit chips with the clock signal provided from an external source along a printed circuit board trace. As clock frequencies have increased, however, it has become more difficult to provide such a high frequency clock signal to the various chips. The problem is magnified on printed circuit boards because the traces begin to exhibit significant reactance at these frequencies.
In order to address this problem, some systems incorporate a phase lock loop (PLL)-based frequency doubler on-chip. Thus if the system on the chip is intended to operate at 50 MHz, for example, the external circuitry need only provide a 25 MHz clock signal which is then doubled by the PLL in order to generate the clock signal for the storage cells on the chip. The use of PLLs is disadvantageous, however, since they typically require the addition of a capacitor and a resistor off-chip, thereby increasing the component count and pin usage.